As deep sub-micron ASIC and IC technology evolves, greater numbers of IC devices are being designed and fabricated with embedded memories. Device testing involves applying a stimulus to a device under test, to acquire the device's response, and to analyze and compare that response with a known good (non-faulty) response.
Embedded memories include a plurality of memory macros, such as RAM memory macros. As these macros are individually accessible during normal system operation, all memory macros potentially may be accessed at the same time. Each macro is surrounded by intervening circuitries including, for example, logic elements, and input/output (I/O) interface circuits. As a result, the embedded macro modules are not directly accessible from the input and output terminals of an integrated circuit chip. Under access conditions, noise can be generated by these circuitries. Therefore, it is important to test the macros under the noisiest of conditions, i.e., when all memory macros are accessed simultaneously.
FIG. 1 show a prior art memory testing system 100 utilizing external automatic test equipment (ATE) 150 for providing the stimulus to the embedded RAM macros 120 of the IC 110. In the embodiment shown in FIG. 1, an external bus structure 140 is required for providing the stimulus from the ATE 150 to each of the I/O pads 130. The tester examines the device response to stimulus and compares it against the known good response that has been stored in the tester as part of the test pattern data. This approach has several disadvantages. In order to allow access to each macro 120, a number of extra pin pads 130 are required. The external bus structure 140 connecting to these numerous pin pads 130 is necessarily very complex. Further, the tester program for the ATE is very complex and thus difficult to program. Still further, the I/O pads 130 often have a limited frequency operating range (e.g., 100 MHz) that is less than the high operating speed (e.g., 200 MHz) of the IC 110. Therefore, tests cannot be run at the true operating speed of the IC 110.
As an alternative to the complex external bus structure 140, complex design-for-test (DFT) circuitry can be employed. Essentially, some of I/O 130 is replaced with intricate databases structures within the IC 110. Due to its complexity, this solution is also unattractive.
Another approach to verifying the corrected operation of an IC device is the built-in self-test (BIST) circuit. BIST circuits place the function of the external, automated tester within the IC chip itself. In a BIST circuit, a finite state machine (FSM) is used to generate stimulus and to analyze the response of the part of the integrated circuit that is under test. The BIST circuitry also interfaces with the higher-level system.
FIG. 2 is a diagram an IC 110A having a plurality of memory macros 120 and a plurality of associated BIST modules 160. One instance of BIST 160 is assigned for each instance of memory macro 120. Through an external trigger, all of the BISTs 160 are caused to operate simultaneously. This approach has significant design concerns, due mostly to the large amount of area overhead that is consumed. Not only do the BIST modules 160 consume area, but they consume routing area resources. The area required for the routing structure connecting each BIST module 160 to its respective memory macro 120 is no longer available for use by other routing resources.
Therefore, improved BIST designs are desired.